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Testing the RAD-CELF

Dave's tutorial to clarify the AD9854 internal register programming is here.

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6/27/17 (Pierre)

css from previous download did not work.

starts from scratch with 4.1.1 obtained from reference in www.github.com/petermilne:

 https://ics-web.sns.ornl.gov/css/

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6/27/17 (Pierre)

• using fan output on ACQ1001 (there are two 12 V fan output on a 2x2 header on the base board)

 set.fanspeed 100

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10/27/16 (Ian)

• measured clock frequency of Vectron: 24.999950 MHz
• measured Clock remap frequency (RADCELF): 25.000020 MHz (DDSC FTW1: 155555555555)
• reprogrammed clock remap to output 24.999950 MHz using dds_prog output (DDSC FTW1: 155552898165)
  • measured clock remap output (RADCELF): 24.999970 MHz
• reprogrammed clock remap to output 24.999930 MHz using dds_prog output (DDSC FTW1: 1555516B2C9E)
  • measured clock remap output (RADCELF): 24.999950 MHz
• adjusted bits for FTW to minimize jitter on scope.
• added 2dB attenuator on output of the old DDS to match specs for AD9512 of the RADCELF and connected it on the radcelf "ext clock"

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10/25/16 (Pierre)

Progress forward testing during October-November: assess performance difference between direct connection of Vectron ultra-low-phase noise OCXO, and clock-remapped Connor-Windfield on-board low-cost OCXO. Tasks:

• connect 25 MHz output (middle SMA on old DDS box, no need to open) to "ext clock" on the RAD-CELF
• add crontab to program the first AD9512 to be, on even days using the clock-remap DDS, and on odd days using directly the Vectron clock
• compare range spectrum and beamforming on even and odd days letting the automated processing active

Task assigments:

• Ian, install and connect the Vectron clock in the old DDS
• Dave advise on signal levels etc... (50 ohm sine wave vs. TTL square wave, is that an issue?)
• Chuy and Isaac, work on crontab to toggle between outside clock and clock remap
• All, look at data produced

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10/15/16 (exchange of email with Dtacq re. channel map

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10/18/16 (Everyone)

DDS B trigger issue

We found that we can no longer use DDS B as a reference for making the trigger pulse at sync P21. It only works now using DDS A

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10/14/16 (Pierre's email & Isaac)

making an acquisition with the A2D

Summarizing Pierre's previous email, the commands we need to make an acquisition are:

          set.site 0 SYS:CLK:FPMUX=FPCLK     % set the external clock 
          set.site 1 trg=1,0,1               % trigger (external, source d0, rising) 
          set.site 1 clk=1,0,1               % clock (external, source d0, rising)
          set.site 1 hi_res_mode 1           % enable high resolution mode
          set.site 1 ACQ43X_SAMPLE_RATE 12207% by setting sampling frequency to 12 KHz 
                                             % clock division (clkdiv) is automatically calculated
          DURATION=500
                                             % launch a time bomb in background
          (sleep $DURATION; set.site 0 set_abort )& 
          nc localhost 4210 > $OUTFILE       % $OUTFILE: directory/filename of the acquisition

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10/14/2016 (Everybody)

Running 100Hz signal generator through the breakout board to the ACQ435 (A2D) board.

Dave's notes here.

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10/13/16 (Isaac & Ian)

DDS interaction with the ACQ435 board

We connected the trigger (UFL connector P21) and the clock (P6 test point) from the RADCELF (DDS) to the ACQ435 (A2D) board. After that...

• We used the AD9854 clock remap (DDS C) to set the clock frequency to 25 MHz:

          echo 004F0041 > /dev/radcelf/ddsC/CR 
          echo 155555555555 > /dev/radcelf/ddsC/FTW1 
          echo 004F0041 > /dev/radcelf/ddsC/CR 

• Then we programmed the AD9512 secondary clock to choose the 25 Mhz from the AD9854 remap:

          set.site 8
          CSPD 02
          UPDATE 01

• After that, we programmed DDS B to create a chirp using the same parameters as Kaka'ako radar (also we change the kp multiplier to 12):

          set.site 2 ddsB_upd_clk_fpga=1
          echo 004F0061 > /dev/radcelf/ddsB/CR 
          echo 172B020C49BA > /dev/radcelf/ddsB/FTW1 
          echo 0000000022E7 > /dev/radcelf/ddsB/DFR 
          echo 01E0A6E0 > /dev/radcelf/ddsB/UCR 
          echo 000001 > /dev/radcelf/ddsB/RRCR 
          echo 0FFF > /dev/radcelf/ddsB/IPDMR 
          echo 0FFF > /dev/radcelf/ddsB/QPDMR 
          echo 004C8761 > /dev/radcelf/ddsB/CR

             Kaka'ako's paramaters:
             radar frequency = 27.3 MHz
             bandwidth = 300 KHz
             chirp length = 0.21 sec

• We checked the trigger pulse just to be sure it was working fine:

          set.site 4 CR 004F8741
          set.site 2 ddsB_upd_clk_fpga=0
          set.site 0 fpctl_sync=b

When looking at the trigger pulse with the scope we noticed there was a little modulation of 25 MHz that corresponds to our clock (I think nothing to worry about).

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10/12/16 (Ryan & Chuy)

CSS (Control System Studio)

• We found that you have to follow the instructions closely from 25.4
• Download from: https://ics-web.sns.ornl.gov/css/products.html
• Use version 3.2.16 then go to "help" menu and update through the program to 4.1.1 (for some reason this worked when downloading 4.1.1 straight did not)
• import http://www.d-tacq.com/swrel/ACQ420FMC-CSS-current.tgz into the workspace and open .project
• After launching go to edit > preferences > CSS App > Display > BOY > OPI runtime and select connection layer: PVmanager (re: instructions: utility PV does not exist??)
• edit > preferences > CSS Core > EPICS > max_array_bytes : 500000
• from the file tree on the left of the workspace select "lia5_complex_launcher_acq420.opi"
• In the green window that shows up look at the top left corner "UUT" set type to acq1001 and serial to 068 (RADCELF/ DDS) or serial 074 (acq435 machine)
• Click "counters" button (just below UUT area) and it should sync with the proper acq1001

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10/12/16 (Isaac & Ian)

Trigger pulse at Sync P21

• We were able to observe and measure the DDS A I/O update stretched chirp pulse on the scope (320 ns). For that we used the UFL connector P21.
  • set.site 4 CR 004F8741
  • set.site 2 ddsA_upd_clk_fpga=0
  • set.site 0 fpctl_sync=b
• The problem is that we cannot see this chirp pulse trough the P12 test point (TRIG A). The reason is that P12 test point is only for input not for output.
• Once we have written:

            set.site 2 ddsA_upd_clk_fpga=0

to see the trigger pulse we cannot change the frequency or enable/disable the chirp. In order to enable chirp mode or modify the frequency we need to set:

            set.site 2 ddsA_upd_clk_fpga=1 

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10/11/16 (Isaac & Ian)

Chirp mode operation

• We found that we should set HOLD to 0 in order to get the chirp. There is a chance that we did not get a chirp since FSK/BPSK/HOLD (PIN 29) was not yet configured to be I/O pin and it is normally high so, chirp was disabled during MODE 3.
• in order to get the actual chirp, CLR ACC1 must be set to HIGH and I/O update is also set to high together CR 004F8761
• frequency keeps ramping up when CLR ACC1 is low and I/O Update Clock is high (CR 004F0761) and CLR is high and I/O Update Clock is low (CR 004F8661)
  • I/O update clock is important which serves as counter after delta frequency back to FTW1 (reference frequency)
    • Thanks for the update, we can program back to to mode 0 without doing master reset or turning it off. :) thanks also for updating the control for BPSK/FSK (Pin 29) and OSK (Pin 30)
    • now we dont have trigger out? we believe it passes through the FPGA. Question is how can be this be outputted given that we are already chirping.

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10/10/16 (Isaac & Ian)

Modifying I and Q amplitudes

• We succeded to modify I and Q levels by setting:
  • OSK (bit 20) in to 1
  • IPDMR values from 1 to 0FFF
  • QPDMR values from 1 to 0FFF
  • CR 004F0661

To change frequency during chirp mode

• Don't enable (bit 0) the I/O Update clock (INT/EXT Update clock) on the CR command
• Go to mode 0 (single freq) and change FTW1
• Go to mode 3 (chirp) or set ACC2 bit to 1 then change FTW1 then ACC2 bit to 0

query to d-tacq about BPSK

• is the BPSK pin on the AD9854 connected to a pin on the FPGA?
• BPSK, i assume is connected to pin29 of ad9854. while in chirp mode, chirping is at halt when set to high.
• tried to toggle the pin using BPSK command, apparently i don't see any difference on this. we want to make sure that this bit is set to low in order to operate in chirp mode

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10/08/16 (Isaac)

Issues while programming the chirp

• We followed instructions to set the DDS in chirp mode. We entered parameters as:
  • FTW1 111111111111 desired frequency (analog to F1 in novatech)
  • DFR 000000000965 delta frequency, increment per DDS step, same units as FTW1 (analog to Fd in novatech)
  • UCR 04a62f80 number of frequency increments in a chirp (analog to Tr in novatech nomenclature)
  • RRCR 000001 ramp rate clock, number of system clock steps per frequency increment minus 1 (analog to Td in novatech)
  • CR 004f0741 configuration bits, in particular, Kp multiplier 15 (1111) and chirp mode 3 (011) (page 24 of RAD-CELF manual)

 00000000 01001111 00000111 01000001

This should give a chirp based at 20 MHz, with 50 kHz bandwidth, length 0.52 s.

Once the chirp mode was "enabled"...

• we actually never saw the chirp.
• the frequency sometimes changed to other values different from the desired one.
• there is no way to change the frequency or executing any other command. While it is true that the values changed in the web page the parameters were never really being executed (as we could see using the scope and the spectrum analyzer).
• we set two DDS with the same frequency and same parameters (but only one in chirp mode) and we noticed there was a drift between them (we saw this connecting channel I from DDS A vs channel I from DDS B to the scope).

As we noticed that after enabling the chirp mode no command was responding we decided to find a way to reset the DDS values to the default. For this purpose we used the following command:

         /usr/local/init/RAD-CELF-init

This actually kind of work in the sense that it resets the frequency but some parameters still remain unchanged in the web page. The question is why they still appear in the web page and why we cannot execute them?

• The only effective way we found to reset the DDS values and the web page was using the command:

     reboot

Still we never saw the chirp

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10/03/16 (Isaac)

We only worked using the Ovened Osc

• We tried to change the frequency of the AD9512 Primary clock from 20 MHz to 10 MHz using the divider by two:

            set.site 7  % enable communication with the AD9512 primary clock 
            DIV1 0000   % disable bypass and divide by 2 for output 1 (AD9854 Remap)
            DIV0 0000   % disable bypass and divide by 2 for output 2 (AD9512 secondary clock)
            UPDATE 01   % execute the last command

• After doing this, we noticed (using the P5 test point) that only the AD9854 Remap changed it's frequency to 10 MHz. The AD9512 Secondary clock (looking at P6 test point) still remained at 20 MHz.
• The solution to set both clocks to 20 MHz was typing:

            set.site 7  % enable communication with the AD9512 primary clock 
            DIV1 0000   % disable bypass and divide by 2 for output 1 (AD9854 Remap)
            DIV0 0000   % disable bypass and divide by 2 for output 2 (AD9512 secondary clock)
            DIV2 0000   % disable bypass and divide by 2 for output 2 (AD9512 secondary clock)
            UPDATE 01   % execute the last command

• Next step consisted in changing the value of the Kp multiplier from 15 to 16:

        set.site 6       % enable communication with the AD9854 Remap
        CR 00500041      % instruction to set Kp to 16 (see page 33 in 
                            AD9854 DDS manual)

• Formula and commands for setting the desired frequency:

        FTW = (Desired Output Frequency × 2^N)/SYSCLK
            = (10MHz x 2^48)/(20MHz x 1/2 x 16)
            = 2^48/2^4
            = 2^44
            = 17592186044416
            = 100000000000 in Hex

            set.site 6    % enable communication with the AD9854 Remap
            FTW1 100000000000 % sets frequency to 10 MHz using Kp multiplier of 16

DDS board: Attach:DDS_Board.jpg Δ Δ

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10/02/2016 (Peter Milne)

how do we modify /etc files in a non-volatile way?

Crude way:

• dump your new etc files in /mnt/local/etc
• add to /mnt/local/rc.user:
• cp /mnt/local/etc/* /etc

You asked about ssh keys? Please use the custom_ssh package. You'll have to mod it to include your keys:

• scp /mnt/local/packages.opt/15-custom_sshkeys-1408301834.tgz to host computer
• untar it
• add your keys
• tar it back up again.
• give it a new name, eg 15-uhi-sshkeys-YYMMDD.tgz
• scp to /mnt/packages

Next boot, it gets unzipped to the right place. You get your new keys, we get to keep our old keys (useful, just in case).

For your entire customization, you have two choices:

• Hack Way:
  • copy a bunch of stuff to /mnt/local
  • copy / execute from /mnt/local/rc.user
• Neat Way
  • make your own package (use 15.custom_sshkeys as an example),
  • install to /mnt/packages
  • unzips and runs init script next boot, at priority of your choosing.

In general, the package way makes for better maintenance, especially when you have a large population, so, recommended.

I'd recommend doing the stuff that really is common in a package, keep only the most limited customization for /mnt/local/rc.user

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9/30/16 (Isaac)

Clocks parameters:

• OX400-620LF Clock (Ovened Osc):

             Frequency = 20MHz
             Pk-Pk voltage = 1.20 V (without 50 Ohms terminator)
             Pk-Pk voltage = 512 mV (50 Ohms terminator)

• External Clock (CLK IN):

             Frequency = 25MHz
             Pk-Pk voltage = 2.15 V (50 Ohms terminator)
             Pk-Pk voltage = 432 mV (3 dBm attenuator + 50 Ohms terminator)

Input Pk-Pk voltage should be less than 2 V

• Commands to control the external clock (clock 1):

            set.site 7  % enable communication with the AD9512 primary clock 
            CSPD 05     % power down clock 2 and enable clock 1 (binary 101)
            UPDATE 01   % execute the last command

• Commands to control the Ovened Osc (clock 2):

            set.site 7  % enable communication with the AD9512 primary clock 
            CSPD 02     % power down clock 1 and enable clock 2 (binary 10)
            UPDATE 01   % execute the last command

• Divider
• in help2 bypass is supposed to be 0080 instead of 8000
• in order to control DIV0 we need to change DIV1 too. Also we need to disable the bypass

Example:

            set.site 7  % enable communication with the AD9512 primary clock 
            DIV1 0000   % disable bypass and divide by 2 for output 1 (AD9854 Remap)
            DIV0 0000   % disable bypass and divide by 2 for output 2 (AD9512 secondary clock)
            UPDATE 01   % execute the last command

• DDS
• formula to set the frequency is explained in page 20 in the AD9854 DDS manual:
  • FTW = (Desired Output Frequency × 2^N)/SYSCLK ; SYSCLK = OX400 crystal frequency x AD9512 Divider x AD9584 Kp multiplier ; SYSCLK<300
• there is no need to type the UPDATE 01 command for executing commands

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9/30/16

• tested how to access the AD9512 and AD9854 from the ACQ1001
• following syntax allows to "login" each chip through SPI interface

       set.site n

• site table

      n=         chip
      4          AD9854-A primary TX
      5          AD9854-B secondary RX
      6          AD9854-C clock remap
      7          AD9512-1 int/ext clock select
      8          AD9512-2 direct/remap clock select

• looked at clock signal with scope.
  • CLK-OUT very dirty, non square. Can clock drive 50 ohms? Or does the RAD-CELF need a line driver out?? (DWH)
  • CLK after AD9512 clean, 1.4 V, able to switch between on-board OCXO and external Vectron

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9/29/16

• created a host NUC following 16.04
• NUC on DHCP appears as 172.16.1.227
• installed the stack RAD-CELF & ACQ-1001-068
• boots as DHCP by default, appeared as 172.16.1.200
• micro-USB connector on ACQ-1001 board provides console, has built-in FTDI ship, when connected to NUC, access console using

      screen /dev/ttyUSB4 115200

• root file system is volatile

      /dev/root                16245     14986       440  97% /

• additional ram file systems

      devtmpfs                513276        24    513252   0% /dev
      tmpfs                   516720        92    516628   0% /dev/shm

• permanent memory appears as

      /dev/mmcblk0p1         3864064    186400   3677664   5% /mnt

• opened browser on the NUC, loaded http://172.16.1.200/ which corresponds to a remount of /dev/shm

      tmpfs                   516720        92    516628   0% /var/www/d-tacq/data

• Temperature button shows Zynq as 57C without fan and 44C with fan
• DDS button yields to http://172.16.1.200/d-tacq/#DDS which has status of all AD9854. No button for status of AD9512
• USB RAD-CELF port takes 32 Gb USB key; formated as ext-4 on the host and mounted with

      mkdir /mnt/usbkey
      mount /dev/sda1 /mnt/usbkey

• NFS mount:

      mkdir /mnt/sunset0
      mount -t nfs -o nolock 172.16.1.9:/export/sunset0 /mnt/sunset0
      mkdir /mnt/nuc
      mount -t nfs -o nolock 172.16.1.227:/home /mnt/nuc

• local options that need to be applied at boot time should be added to

      /mnt/local/rc.user

Processor characteristics: