Revision History

MODULE_TYPE	MODULE_VERSION	FPGA_REVISION	Date	Notes
x"69"	x"00"	x"0001"	20th July 2016	Initial Version
x"69"	x"00"	x"0002"	10th October 2016	Updates for local byte bang SPI interface rather than ZYNQ PS SPI

The RAD_CELF is a hybrid device hence the module type 69 with both Digital Out and Digital In
The Digital I/O is both a series of simple control pins on the DDS devices and inputs from these devices in addition to a number of SPI bus connections to the DDS and Clock control devices
Also present on the board are digital I/O in the form of I2C devices and Analog Input from an I2C device

By default the Module outputs the DDS input clock onto the Clock Bus bit 3, the ACQ435 ADC board in the system should be configured to use this clock as the Sigma-Delta Clock
The 3 DDS Output Clocks can also be observed on the standard Clock Bus, the full use of the Clock Bus is as follows
CLOCK_BUS(3) - Standard RAD CELF Clock - Main Clock - this is the clock that the two main DDS devices use as the input to their REFCLCK
CLOCK_BUS(4) - DDS A Comparator Output Clock
CLOCK_BUS(5) - DDS B Comparator Output Clock
CLOCK_BUS(6) - DDS C Comparator Output Clock
Two ADC Triggers are present on this board that are connected to the Trigger and Sync Busses - this may change